1. Field of the Invention
The present invention relates to a semiconductor memory device such as a flash EEPROM (Electrically Erasable and Programmable Read Only Memory) having a floating gate electrode, a control gate electrode, and an erase gate electrode and to a manufacturing method therefor.
2. Prior Art
As an electrically writable non-volatile memory, a flash EEPROM has been well known. The flash EEPROM has such a structure that a floating gate electrode is formed via a gate insulating film on a channel region interposed between source and drain regions formed in a semiconductor substrate and a control gate electrode is further formed via a gate insulating film on the floating gate electrode. A write operation to the flash EEPROM is performed by generating hot electrons in the channel region adjacent to the drain of the semiconductor substrate with the application of a high voltage to the drain region and to the control gate electrode and injecting the hot electrons under acceleration into the floating gate electrode. To perform an erase operation to the flash EEPROM, there has recently been adopted a method in which the floating gate electrode is caused to emit electrons to the source or drain region or to the channel region via the gate insulating film by using a tunneling phenomena or a method using an erase gate electrode formed on the floating gate electrode via tunneling insulating films, in which electrons are caused to tunnel from the floating gate electrode to the erase gate electrode with the application of an erase voltage to the erase gate electrode.
As extreme miniaturization, higher integration, and higher performance has been required of semiconductor memory devices in recent years, extreme miniaturization and higher performance has also been required more urgently of the foregoing electrically erasable flash EEPROM. In particular, a reduction in the film thickness of a memory cell and a reduction in the height difference between a MOS transistor composing a peripheral circuit (hereinafter referred to as a "peripheral transistor") and the memory cell have been in growing demand to achieve extreme miniaturization.
As a method of reducing the height difference between the peripheral transistor and the memory cell, there has conventionally been known one using a step-height reducing mask. In accordance with the method, the height difference between the peripheral transistor and the memory cell can be reduced by using the step-height reducing mask which is formed with an aperture corresponding to a portion having a large step height, such as the memory cell, compared with the semiconductor substrate and the peripheral portion.
Referring to FIGS. 15 to 23, a flash EEPROM as a conventional semiconductor memory device will be described.
FIG. 15 is a plan view of a memory cell area in the conventional semiconductor memory device. FIG. 16 is a cross-sectional view taken along the line III-III' of FIG. 15. FIG. 17 is a cross-sectional view taken along the line IV-IV' of FIG. 15.
As shown in FIGS. 15 to 17, the conventional semiconductor memory device comprises: source/drain regions 1 of a memory cell formed in a specified region of a semiconductor substrate 2; an insulating film 5 for element isolation; first and second insulating films 6 and 8 each forming a gate insulating film; a floating gate electrode 7; a control gate electrode 9; a first interlayer insulating film 12 composed of a third insulating film 10 and sidewall insulating films 11; tunneling insulating films 13; and an erase gate electrode 15.
A description will be given to a method of manufacturing the conventional semiconductor memory device thus constituted with reference to FIGS. 18 to 23, which are cross-sectional views illustrating process steps in accordance with the manufacturing method. It is to be noted that the memory cell area in FIGS. 18 to 23 shows a cross-sectional portion taken along the line IV-IV' of FIG. 15.
First, as shown in FIG. 18, the source/drain regions 1 (see FIGS. 15 and 16) are formed in specified regions of the memory cell area in a main surface of the semiconductor substrate 2. After the insulating film 3 is formed over the main surface of the semiconductor substrate 2, a mask pattern 4 is formed from a photoresist by using a lithographic technique.
Next, as shown in FIG. 19, the insulating film 5 for element isolation is formed by anisotropic etching and then the mask pattern 4 formed of the photoresist is removed.
Next, as shown in FIG. 20, a first insulating film 6 is formed by a thermal oxidation process and then a first polysilicon film is deposited by a CVD process. The first polysilicon film is masked and formed into stripes elongated along the cross section taken along the line IV-IV' (FIG. 15) by etching. Subsequently, the second insulating film 8 is formed by a thermal oxidation process and then a second polysilicon film and an insulating film are deposited by a CVD process. The resulting structure is masked and subjected to anisotropic etching to form the third insulating film 10 and the control gate electrode 9. Thereafter, the sidewall insulating films 11 are formed by using a known technique. Hereinafter, the combination of the third insulating film 10 and the sidewall insulating films 11 will be termed the first interlayer insulating film 12. Then, the first polysilicon film is etched by an anisotropic etching technique using the first interlayer insulating film 12 as a mask to form the floating gate electrode 7. In FIG. 20, the memory cell area in which memory cells are to be formed is designated at A, while a peripheral circuit area in which a peripheral circuit is to be formed is designated at B.
Next, as shown in FIG. 21, the tunneling insulating films 13 and the gate insulating film 14 of a peripheral transistor are formed by a thermal oxidation process, followed by a third polysilicon film deposited thereon by a CVD process. The third polysilicon is then masked and subjected to anisotropic etching, thereby forming the erase gate electrode 15 in the memory cell area A and the gate electrode 16 of the peripheral transistor in the peripheral circuit area B. Subsequently, arsenic is implanted into the peripheral circuit area B by using a mask formed with an aperture corresponding to the specified source/drain regions of the peripheral transistor, thereby forming the source/drain regions 17 of the peripheral transistor and completing the formation of the memory cell and the peripheral transistor.
Next, as shown in FIG. 22, a second interlayer insulating film 18 is deposited by the process of atmospheric pressure CVD and subjected to anisotropic etching after a photoresist 19 is formed by using a step-height reducing mask formed with an aperture corresponding to a portion with a large step height, such as the memory cell. Subsequently, the photoresist 19 is removed and annealing treatment is performed to form a planarized interlayer insulating film 20, as shown in FIG. 23. Thus, in the conventional manufacturing method, the stepped underlie is planarized to facilitate patterning in the subsequent wiring step and the interlayer insulating film is planarized by using the step-height reducing mask after the formation of the memory cell.
According to the conventional structure and manufacturing method, the insulating film 5 for element isolation has a uniform thickness since it is formed simultaneously for use in the memory cell area and in the peripheral circuit area. On the other hand, the total film thickness a.sub.2 of the memory cell is three times the total thickness b.sub.2 of the peripheral transistor or more since, in the memory cell area A, the floating gate electrode 7 is formed continuously over the first insulating film 6 and the end portions of the insulating films 5 for element isolation located on both sides thereof and the control gate electrode 9 and the erase gate electrode 15 are formed on the floating gate electrode 7, as shown in FIG. 21. Moreover, the total film thickness of the floating gate electrode 7, the control gate electrode 9, and the erase gate electrode 15 is dependent on the step height of the underlying layer since, to perform precise pattern formation for these electrodes, it is required to deposit a polysilicon film to such a thickness as to eliminate the height difference in the underlying layer prior to etching. As the step height of the underlying layer is larger, the film thickness should be larger. As the step height of the underlying layer is larger, the formation of the pattern on the underlying layer becomes more difficult.
For example, the difference (a.sub.2 -b.sub.2) between the total film thickness a.sub.2 of the memory cell and the total film thickness b.sub.2 of the peripheral transistor is increased in the wiring step subsequent to the formation of the memory cell and the peripheral transistor as shown in FIG. 21, resulting in an increased height difference between the memory cell area A and the peripheral circuit area B. Unless planarization is performed by using the step-height reducing mask after the deposition of the second interlayer insulating film 18 as shown in FIG. 22, a sufficient margin is no more allowed for focal depth during wire patterning, which renders the formation of a wiring pattern difficult. Hence, the stepped underlie should be planarized by using the step-height reducing mask.